CMC Microsystems
CMC Workshops and Training

Cadence RF System-in-Package Methodology Training

The RF SiP implementation methodology provides a new packaging platform with the advantages of high flexibility, lower cost, and faster cycle time than SoC implementations. SiP technology enables integration of digital and logic ICs, RF ICs, and passives into a single package in a cost-effective process.

 

The lack of a complete design flow including design tool interaction between design domains and an underlying methodology has been identified as a key requirement to fully leverage the advantages SiP offers. Developers will be able to remove weeks or months from their RF product design process through the combination of best practices and the deployment of the proposed co-design methodology and associated technology platform. These best practices, and the proposed co-design methodology and associated technology platform are the basis for this Cadence RF SiP Methodology training. 

  

The agenda proposed for this 3 day RF-SiP kit training is organized in a fashion that will beign with exposing participants to the SiP front-end design and simulation tasks done in the Virtuoso environment.  The course will then cover the SiP back-end design tasks done in SiP layout environment and then conclude with a demonstration on how to design a power amplifier module (front-end & back-end) using the complete RF-SiP design flow.

 

 

RF SiP Methodology Kit training agenda: Download

 

RF SiP Design Methodology and Flow white paper: Download 

 

 

Agenda 

 

 

Day 1

 

9:00am-5:00pm (Lunch to be Included)

  • RF-SiP kit Introduction & Demo
  • Module 1: RF-SiP Design Flow & Methodology
  • Module 2: Design Environment & Infrastructure
  • Module 3: RF-SiP Front-End Design
  • Module 4: Off-Chip Component Design

 Day 2

9:00am-5:00pm (lunch to be Included)

  • Module 5: Preliminary SiP Placement & Floorplan
  • Module 7: SiP Layout Finishing
  • Module 8: Post-Layout Extraction for Re-Simulation
  • Module 9: Physical Design & Assembly Sign-Off
  • Module 10: Links to Manufacturing

Day 3

9:00am-5:00pm (Lunch to be Included)

  • Module 6: RF Module Design
  • Q&A

 Date Site  Register Now. 
 May 12-14, 2010  

University of Toronto 

Sandford Fleming Bldg.

Room: 2204 Building Map

Completed
 May 17-19, 2010

Ecole Polytechnique

VLSI Pavillon Mackay-Lassonde,

Room: L-5904

Completed
 June 9-11, 2010
University of Calgary

Lab # ICT 218 (please note change)

registrar@cmc.ca
 June 14-16, 2010 University of British Columbia

Room: #358 McLoad Builidng, 2356 Main Hall Vancouver, BC

http://www.maps.ubc.ca/PROD/index_detail.php?locat1=312


registrar@cmc.ca

 

Registration Details:

Registration is now open for these 3 day training sessions.  Space is limited for this course and will be offered on a first come first serve basis so please sign up early.

Cost: $2000.00CDN

Researchers at Canadian Academic institutions who are CMC Subscribers (Designer or Prototyping Level) are eligible for:

  • 80% discount off list price (cost becomes $400.00CDN )
  • Financial Assistance for Travel also available.  Details
  • CMC Travel Claim Form. Download

 Learn More about Subscriptions.